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@@ -29,6 +29,7 @@ from cc1101.addresses import (
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StrobeAddress,
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ConfigurationRegisterAddress,
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StatusRegisterAddress,
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+ PatableAddress,
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FIFORegisterAddress,
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)
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from cc1101.options import PacketLengthMode, SyncMode, ModulationFormat
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@@ -149,6 +150,9 @@ class CC1101:
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# > in the 300-348 MHz, 387-464 MHz and 779-928 MHz bands.
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_TRANSMIT_MIN_FREQUENCY_HERTZ = 281.7e6
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+ # > The PATABLE is an 8-byte table that defines the PA control settings [...]
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+ _PATABLE_LENGTH_BYTES = 8
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+
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def __init__(
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self, spi_bus: int = 0, spi_chip_select: int = 0, lock_spi_device: bool = False
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) -> None:
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@@ -211,7 +215,9 @@ class CC1101:
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def _read_burst(
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self,
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- start_register: typing.Union[ConfigurationRegisterAddress, FIFORegisterAddress],
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+ start_register: typing.Union[
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+ ConfigurationRegisterAddress, PatableAddress, FIFORegisterAddress
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+ ],
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length: int,
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) -> typing.List[int]:
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response = self._spi.xfer([start_register | self._READ_BURST] + [0] * length)
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@@ -243,7 +249,9 @@ class CC1101:
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def _write_burst(
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self,
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- start_register: typing.Union[ConfigurationRegisterAddress, FIFORegisterAddress],
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+ start_register: typing.Union[
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+ ConfigurationRegisterAddress, PatableAddress, FIFORegisterAddress
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+ ],
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values: typing.List[int],
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) -> None:
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_LOGGER.debug(
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@@ -457,6 +465,12 @@ class CC1101:
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)
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self._set_preamble_length_index(int(index))
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+ def _get_power_amplifier_setting_index(self) -> int:
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+ """
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+ see ._set_power_amplifier_setting_index
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+ """
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+ return self._read_single_byte(ConfigurationRegisterAddress.FREND0) & 0b111
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+
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def _set_power_amplifier_setting_index(self, setting_index: int) -> None:
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"""
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FREND0.PA_POWER
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@@ -774,6 +788,23 @@ class CC1101:
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start_register=ConfigurationRegisterAddress.PKTCTRL0, values=[pktctrl0]
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)
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+ def _get_patable(self) -> typing.Tuple[int, ...]:
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+ """
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+ see "10.6 PATABLE Access" and "24 Output Power Programming"
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+
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+ default: (0xC6, 0, 0, 0, 0, 0, 0, 0)
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+ """
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+ return tuple(
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+ self._read_burst(
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+ start_register=PatableAddress.PATABLE, length=self._PATABLE_LENGTH_BYTES
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+ )
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+ )
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+
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+ def _set_patable(self, setting: typing.Iterable[int]):
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+ setting = list(setting)
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+ assert 0 < len(setting) <= self._PATABLE_LENGTH_BYTES, setting
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+ self._write_burst(start_register=PatableAddress.PATABLE, values=setting)
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+
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def _flush_tx_fifo_buffer(self) -> None:
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# > Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
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_LOGGER.debug("flushing tx fifo buffer")
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