added method _get_patable

cc1101/__init__.py

@@ -29,6 +29,7 @@ from cc1101.addresses import (
     StrobeAddress,
     ConfigurationRegisterAddress,
     StatusRegisterAddress,
+    PatableAddress,
     FIFORegisterAddress,
 )
 from cc1101.options import PacketLengthMode, SyncMode, ModulationFormat
@@ -108,6 +109,9 @@ class _ReceivedPacket:  # unstable
         )
 
 
+_PatableSetting = typing.Tuple[int, ...]
+
+
 class CC1101:
 
     # pylint: disable=too-many-public-methods
@@ -149,6 +153,9 @@ class CC1101:
     # > in the 300-348 MHz, 387-464 MHz and 779-928 MHz bands.
     _TRANSMIT_MIN_FREQUENCY_HERTZ = 281.7e6
 
+    # > The PATABLE is an 8-byte table that defines the PA control settings [...]
+    _PATABLE_LENGTH_BYTES = 8
+
     def __init__(
         self, spi_bus: int = 0, spi_chip_select: int = 0, lock_spi_device: bool = False
     ) -> None:
@@ -211,7 +218,9 @@ class CC1101:
 
     def _read_burst(
         self,
-        start_register: typing.Union[ConfigurationRegisterAddress, FIFORegisterAddress],
+        start_register: typing.Union[
+            ConfigurationRegisterAddress, PatableAddress, FIFORegisterAddress
+        ],
         length: int,
     ) -> typing.List[int]:
         response = self._spi.xfer([start_register | self._READ_BURST] + [0] * length)
@@ -774,6 +783,18 @@ class CC1101:
             start_register=ConfigurationRegisterAddress.PKTCTRL0, values=[pktctrl0]
         )
 
+    def _get_patable(self) -> _PatableSetting:
+        """
+        see "10.6 PATABLE Access" and "24 Output Power Programming"
+
+        default: (0xC6, 0, 0, 0, 0, 0, 0, 0)
+        """
+        return tuple(
+            self._read_burst(
+                start_register=PatableAddress.PATABLE, length=self._PATABLE_LENGTH_BYTES
+            )
+        )
+
     def _flush_tx_fifo_buffer(self) -> None:
         # > Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
         _LOGGER.debug("flushing tx fifo buffer")

cc1101/addresses.py

@@ -87,6 +87,11 @@ class StatusRegisterAddress(enum.IntEnum):
     RCCTRL0_STATUS = 0x3D  # Last RC oscillator calibration result
 
 
+class PatableAddress(enum.IntEnum):
+    # see "10.6 PATABLE Access"
+    PATABLE = 0x3E
+
+
 class FIFORegisterAddress(enum.IntEnum):
     # see "10.5 FIFO Access"
     # > When the R/W-bit is zero, the TX FIFO is accessed,

tests/config/test_0x3e_patable.py

@@ -0,0 +1,34 @@
+# python-cc1101 - Python Library to Transmit RF Signals via CC1101 Transceivers
+#
+# Copyright (C) 2020 Fabian Peter Hammerle <fabian@hammerle.me>
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+import pytest
+
+# pylint: disable=protected-access
+
+
+@pytest.mark.parametrize(
+    "patable",
+    (
+        (198, 0, 0, 0, 0, 0, 0, 0),  # default
+        (0, 198, 0, 0, 0, 0, 0, 0),  # OOK
+        (1, 2, 3, 4, 5, 6, 7, 8),
+    ),
+)
+def test__get_patable(transceiver, patable):
+    transceiver._spi.xfer.return_value = [0] + list(patable)
+    assert transceiver._get_patable() == patable
+    transceiver._spi.xfer.assert_called_once_with([0x3E | 0xC0] + [0] * 8)