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addresses.py 3.7 KB

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  1. import enum
  2. class StrobeAddress(enum.IntEnum):
  3. # see "Table 42: Command Strobes"
  4. SRES = 0x30
  5. SFSTXON = 0x31
  6. SXOFF = 0x32
  7. SCAL = 0x33
  8. SRX = 0x34
  9. STX = 0x35
  10. SIDLE = 0x36
  11. SWOR = 0x38
  12. SPWD = 0x39
  13. SFRX = 0x3A
  14. SFTX = 0x3B
  15. SWORRST = 0x3C
  16. SNOP = 0x3D
  17. class ConfigurationRegisterAddress(enum.IntEnum):
  18. # see "Table 43: Configuration Registers Overview"
  19. IOCFG2 = 0x00 # GDO2 output pin configuration
  20. IOCFG1 = 0x01 # GDO1 output pin configuration
  21. IOCFG0 = 0x02 # GDO0 output pin configuration
  22. FIFOTHR = 0x03 # RX FIFO and TX FIFO thresholds
  23. SYNC1 = 0x04 # Sync word, high byte
  24. SYNC0 = 0x05 # Sync word, low byte
  25. PKTLEN = 0x06 # Packet length
  26. PKTCTRL1 = 0x07 # Packet automation control
  27. PKTCTRL0 = 0x08 # Packet automation control
  28. ADDR = 0x09 # Device address
  29. CHANNR = 0x0A # Channel number
  30. FSCTRL1 = 0x0B # Frequency synthesizer control
  31. FSCTRL0 = 0x0C # Frequency synthesizer control
  32. FREQ2 = 0x0D # Frequency control word, high byte
  33. FREQ1 = 0x0E # Frequency control word, middle byte
  34. FREQ0 = 0x0F # Frequency control word, low byte
  35. MDMCFG4 = 0x10 # Modem configuration
  36. MDMCFG3 = 0x11 # Modem configuration
  37. MDMCFG2 = 0x12 # Modem configuration
  38. MDMCFG1 = 0x13 # Modem configuration
  39. MDMCFG0 = 0x14 # Modem configuration
  40. DEVIATN = 0x15 # Modem deviation setting
  41. MCSM2 = 0x16 # Main Radio Control State Machine configuration
  42. MCSM1 = 0x17 # Main Radio Control State Machine configuration
  43. MCSM0 = 0x18 # Main Radio Control State Machine configuration
  44. FOCCFG = 0x19 # Frequency Offset Compensation configuration
  45. BSCFG = 0x1A # Bit Synchronization configuration
  46. AGCTRL2 = 0x1B # AGC control
  47. AGCTRL1 = 0x1C # AGC control
  48. AGCTRL0 = 0x1D # AGC control
  49. WOREVT1 = 0x1E # High byte Event 0 timeout
  50. WOREVT0 = 0x1F # Low byte Event 0 timeout
  51. WORCTRL = 0x20 # Wake On Radio control
  52. FREND1 = 0x21 # Front end RX configuration
  53. FREND0 = 0x22 # Front end TX configuration
  54. FSCAL3 = 0x23 # Frequency synthesizer calibration
  55. FSCAL2 = 0x24 # Frequency synthesizer calibration
  56. FSCAL1 = 0x25 # Frequency synthesizer calibration
  57. FSCAL0 = 0x26 # Frequency synthesizer calibration
  58. RCCTRL1 = 0x27 # RC oscillator configuration
  59. RCCTRL0 = 0x28 # RC oscillator configuration
  60. FSTEST = 0x29 # Frequency synthesizer calibration control
  61. PTEST = 0x2A # Production test
  62. AGCTEST = 0x2B # AGC test
  63. TEST2 = 0x2C # Various test settings
  64. TEST1 = 0x2D # Various test settings
  65. TEST0 = 0x2E # Various test settings
  66. class StatusRegisterAddress(enum.IntEnum):
  67. # see "Table 44: Status Registers Overview"
  68. PARTNUM = 0x30 # Part number for CC1101
  69. VERSION = 0x31 # Current version number
  70. FREQEST = 0x32 # Frequency Offset Estimate
  71. LQI = 0x33 # Demodulator estimate for Link Quality
  72. RSSI = 0x34 # Received signal strength indication
  73. MARCSTATE = 0x35 # Control state machine state
  74. WORTIME1 = 0x36 # High byte of WOR timer
  75. WORTIME0 = 0x37 # Low byte of WOR timer
  76. PKTSTATUS = 0x38 # Current GDOx status and packet status
  77. VCO_VC_DAC = 0x39 # Current setting from PLL calibration module
  78. TXBYTES = 0x3A # Underflow and number of bytes in the TX FIFO
  79. RXBYTES = 0x3B # Overflow and number of bytes in the RX FIFO
  80. RCCTRL1_STATUS = 0x3C # Last RC oscillator calibration result
  81. RCCTRL0_STATUS = 0x3D # Last RC oscillator calibration result
  82. class FIFORegisterAddress(enum.IntEnum):
  83. # see "10.5 FIFO Access"
  84. # > When the R/W-bit is zero, the TX FIFO is accessed,
  85. # > and the RX FIFO is accessed when the R/W-bit is one.
  86. TX = RX = 0x3F