added method `disable_checksum()` to disable automatic CRC sum appending in TX and checking in RX mode

CHANGELOG.md

@@ -5,6 +5,9 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
+### Added
+- method `disable_checksum()` to disable automatic CRC sum
+  appending in TX mode and checking in RX mode
 
 ## [1.0.0] - 2020-09-02
 ### Added

cc1101/__init__.py

@@ -428,6 +428,21 @@ class CC1101:
             start_register=ConfigurationRegisterAddress.PKTCTRL0, values=[pktctrl0]
         )
 
+    def disable_checksum(self) -> None:
+        """
+        PKTCTRL0.CRC_EN
+
+        Disable automatic 2-byte cyclic redundancy check (CRC) sum
+        appending in TX mode and checking in RX mode.
+
+        See "Figure 19: Packet Format".
+        """
+        pktctrl0 = self._read_single_byte(ConfigurationRegisterAddress.PKTCTRL0)
+        pktctrl0 &= 0b11111011
+        self._write_burst(
+            start_register=ConfigurationRegisterAddress.PKTCTRL0, values=[pktctrl0]
+        )
+
     def _get_transceive_mode(self) -> _TransceiveMode:
         pktctrl0 = self._read_single_byte(ConfigurationRegisterAddress.PKTCTRL0)
         return _TransceiveMode((pktctrl0 >> 4) & 0b11)

examples/transmit.py

@@ -11,6 +11,7 @@ with cc1101.CC1101() as transceiver:
     transceiver.set_base_frequency_hertz(433.5e6)
     transceiver.set_symbol_rate_baud(600)
     # transceiver.set_sync_mode(cc1101.SyncMode.NO_PREAMBLE_AND_SYNC_WORD)
+    # transceiver.disable_checksum()
     print(transceiver)
     print("state", transceiver.get_marc_state().name)
     print("base frequency", transceiver.get_base_frequency_hertz(), "Hz")